Hardware Timer

A hardware timer is a time tracking peripheral that runs independent of the foreground CPU instructions. For example, you can start to count the clock cycles using a hardware timer independent of the instructions the CPU is processing. Fundamentally, a hardware timer is a CPU peripheral, but you can consider "CPU peripheral" as an independent CPU, or co-processor.


Part 0: Fundamentals

Objective of this part is to fully understand the clock system, and the registers of the Timer Peripheral.

First thing to recognize is that all peripherals are configured to receive the PLL clock. As a reminder, 12MHz clock on the SJ2 (NXP chip) is multiplied to 96MHz, and this clock is then sourced to the hardware timer peripheral. What this means is that you can digitally count the number of clock cycles of the CPU which is 96Mhz, and each timer register ticking up (or incrementing) is at the rate of about 10.4ns.

The LPC User manual chapter of interest is:

The register of relevance:

  • PC
    • This register will count the input clock which is the PCLK (peripheral clock)
    • When it equals to the value of (PR + 1) then it resets back down to zero, and increment TC by 1
  • PR
    • This register provides means to divide the clock, and increment the TC register slower than the input clock of 96Mhz. So for example, if (PR == 95), then input clock of 96Mhz will increment the PC register, and when that equals to 95, the TC will increment by 1. So in this example, we will configure such that TC register will increment at 1Mhz rather than 96MHz
  • Match Registers
    • When TC matches one of the four registers, you can generate events such as resetting the timer
  • Capture Registers
    • These allow you to capture events such as an external GPIO (switch or a sensor) giving data by means of signal pulses. The capture registers can capture the time when a GPIO goes low, or it goes high, and in the end you can use this peripheral to read pulse width modulation signals